A current common requirement for an electronic circuit and particularly for electronic circuits manufactured as integrated circuits in semiconductor processes is an array of memory storage elements. These elements may be provided as static random access memory cells (SRAM) cells to form SRAM memories. SRAM memory cells are described as “volatile” memory, because if the power to the integrated circuit device including the SRAM cells is removed, the stored data will be lost. Each bit cell in an SRAM array is a latch formed of typically six transistors (6T) or more such as 8T or 10T cells. Due to the reinforcing operation of the latch circuits, the SRAM cells will retain stored data so long as a sufficient supply voltage is present. SRAM memory arrays also have fast cell access times, making SRAM memories particularly attractive as scratchpad storage, or working data storage, such as in cache memory for processors. Recent system on a chip (SOC) designs often incorporate one or more “cores” with SRAM memory. These cores are often predesigned popular processors such as DSPs, ARMs, RISC, microcontrollers, or microprocessors. For example the processor cores may be arranged with a level one (L1) cache memory of SRAM cells laid out near or adjacent to the processor on a semiconductor substrate, to make very fast processing operations possible.
Increasingly, integrated circuits are used in battery operated and portable devices. For example, SOCs may be used to provide all or most of the circuitry needed to implement the main functions of a cellphone, laptop computer, netbook computer, tablet computer, audio or video player, camcorder or camera, smartphone or PDA, or GPS device. SRAM arrays are often combined with a processor and user logic to provide these functions in a single integrated circuit, in a stacked die packaged as a single device, or in a stacked wafer package, or in a package-on-package (PoP) device. Use of these highly integrated devices increases the system board area available and reduces the design and engineering development time needed to create new devices.
In an SRAM cell, data is stored on two storage nodes which are inversely related, which are referred to herein as the cell “data node” and the “data bar node”. The storage portion of the SRAM cell may be formed from four MOS transistors, arranged as a latch circuit of two cross coupled inverters, each storage node being formed at the gate terminals of two MOS transistors and receiving the output of an inverter formed of the other two MOS transistors. Typically the circuit is implemented in complementary MOS (CMOS) technology. A pass gate coupled as a transfer gate provides an input and output path for a data on a bit line, and data on a complementary bit line bar, to be written to the data node and the data node bar, respectively. Read data is passed from the data node, and the data node bar, to the corresponding bit lines. The bit lines are coupled to the data nodes by an active voltage on a word line coupled to the gate terminals on the two pass gates.
Current semiconductor processes continue to shrink the features of the SRAM cells which leads to increased contact resistance, reduced contact hole size, and reduced tolerances in the photolithography used to form the SRAM structures. In addition, multiple patterning steps are required in the photolithography processing to form the SRAM cell structures, which increases costs and lowers throughput of the manufacturing processes.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.